The present invention relates to control devices of disk array devices for storing data in a plurality of magnetic disk devices.
In view of the fact that the input/output (I/O) performance or throughput of a disk subsystem (referred to as a xe2x80x9csubsystemxe2x80x9d hereinafter) is less by approximately three to four orders of magnitude than the I/O throughput of main memories of computers which use semiconductor memory devices as their storage media, attempts have conventionally been made to reduce this difference, namely, to improve the I/O throughput of the subsystem. One prior known approach to improving the subsystem""s I/O throughput is to use a system, called a xe2x80x9cdisk arrayxe2x80x9d, for constituting the subsystem from a plurality of magnetic disk devices, such as fixed or xe2x80x9chardxe2x80x9d disk drives (HDDs), which are applicable for use in storing data.
FIG. 2 shows an arrangement typical of one known type of disk array. This includes a plurality of channel interface (IF) units 411 for execution of data transmission between a mainframe 50 and a disk array controller 2, a plurality of disk IF units 414 for execution of data transfer between HDDs 20 and the disk array control unit 2, a cache memory unit 14 for temporarily storing data of the HDDs 20, and a shared memory unit 15 for storing control information relevant to the disk array controller 2 (for example, information concerning data transfer control between the channel units 411 and disk IF units 414 and the cache memory unit 14), wherein the cache memory unit 14 and shared memory unit 15 are arranged so that they are accessible from all of the channel IF units 411 and disk IF units 414. With this disk array, the channel IF units 411 and disk IF units 414 are connected to the shared memory unit 15 on a one-to-one basis; similarly, the channel IF units 411 and disk IF units 414 are connected one by one to the cache memory unit 14. This connection form is called a star connection.
The channel IF unit 411 has an interface for connection with the mainframe 50 and also a microprocessor (not shown) for controlling input/output with respect to the mainframe 50. The disk IF unit 414 has an interface for connection to the HDDs 20 and a microprocessor (not shown) for controlling input/output relative to HDDs 20. The disk IF unit 414 also executes RAID functions.
FIG. 3 shows the configuration of another known disk array. It includes a plurality of channel IF units 411 for execution of data transfer between a mainframe 50 and a disk array controller 3, a plurality of disk IF units 414 for execution of data transfer between HDDs 20 and the disk array controller 3, a cache memory unit 14 for temporarily storing data of the HDDs 20, and a shared memory unit 15 for storing control information relevant to the disk array controller 3 (e.g. information concerning data transfer control between the channel units 411 and disk IF units 414 and the cache memory unit 14), wherein each of the channel IF units 411 and disk IF units 414 is connected by a shared bus 130 to the shared memory unit 15; whereas, each channel unit 411 and disk IF unit 414 is connected by a shared bus 131 to the cache memory unit 14. Such a connection form is called a shared bus connection.
In order to make the architecture of a disk array scalable, the number of disk IF units must be increased according to the capacity of the disk (the number of logical volumes) connected to a disk controller. In addition, the number of channel IF units in the object disk array controller must be increased according to the necessary number of channels connected to the host computer. For a disk array controller that employs the shared bus connection form, however, increasing the number of channel IF units and disk IF units degrades the data transfer throughput of the access path between each of the channel IF units and/or the disk IF units and a cache memory unit or a shared memory unit which is to become scalable according to an increase in the number of channel IF units or disk IF units. This is because the shared bus becomes a bottleneck in making the access path throughput scalable.
Furthermore, in the case of the shared bus connection form, if a high performance microprocessor is employed for each of those channel IF units and/or the disk IF units, the transfer capacity of the shared bus cannot cope with the processor performance, thereby the shared bus can hardly keep up with the high speed operation of the processor.
Furthermore, in the case of the shared bus connection form, if an operation error occurs in any of those channel IF units (or disk IF units) connected to the shared bus, it is difficult to identify the error-detected channel IF unit (or disk IF unit).
On the contrary, in the disk array controller of the star connection form, it is possible to increase the internal path performance or throughput in a way proportional to the number of access paths being connected to either the shared memory unit or cache memory unit, which in turn makes it possible to increase the throughput of the internal paths in accordance with the add-in reconfiguration of the channel and disk IF units or alternatively with the performance of the processors being used. In addition, since the star connection is used between the channel IF and disk IF units and the cache memory unit or between the channel and disk IF units and the shared memory unit, it is easy to specify a channel IF unit (or disk IF unit) at which an operation failure has occurred.
In the disk array controller of the star connection form, increasing the number of those channel IF units or disk IF units which are built therein would result in an increase in the number of access paths between the channel and disk IF units and the cache memory unit and between the channel and disk IF units and the shared memory unit. Additionally, the throughput called for by disk array control devices tends to further increase due to employment of high-speed channels, such as a fiber optic channel, for connection between host computers and disk array controllers; therefore, in order to satisfy this need for improvement of the throughput, it should be effective to increase the number of access paths between the channel and the disk IF units and the cache memory unit and between the former and the shared memory unit to thereby improve the internal path throughput.
However, the amount of data in a single data segment or datum to be stored in the cache memory is much greater than the amount of data in a single control information item being stored in the shared memory. As an example, in a disk control device connected to a mainframe, a single datum being stored in the cache memory is several kilobytes (KB) or more or less (for example, 2 KB), whereas one control information item stored in the shared memory is several bytes or therearound (e.g. 4 bytes). As another example, in disk control devices connected to host computers of open architectures, a single datum as stored in the cache memory is several tens of bytes (e.g. 64 bytes), whereas a single control information item stored in the shared memory is about several bytes (e.g. 4 bytes). Accordingly, the amount of data to be transferred between the channel and the disk IF units and the cache memory unit is extremely greater than the amount of data being transferred between the channel and disk IF units and the shared memory unit, which leads to a need for letting the data width of an access path between the channel and disk IF units and the cache memory unit be wider than the data width of an access path between the channel and disk IF units and the shared memory unit. For instance, the access path of the former is constituted from a 16-bit width bus, whereas the latter is constituted from a 4-bit width bus. For this reason, increasing the line number of access paths between the channel and disk IF units and the cache memory unit would result in creation of a problem of shortage of the number of pins in an LSI(s) of the cache memory unit and shortage of the number of pins in a connector of the cache memory unit package for connection of the access paths thereof.
On the other hand, in order to reduce the response time from the disk array controller to the host computer, the time of access to the control information stored in the shared memory must also be as short as possible.
Furthermore, along with the spread of open systems in recent years, storage sub-systems supporting a multi-platform are now high on the wish list. Concretely, the same disk array controller must be used to support such fast interfaces as fiber optic channels, etc. and such slow interfaces for ESCON (Enterprise Systems Connection: ESCON is a registered trademark of International Business Machines USA, Corp.)) channels whose throughput is as slow as several tens of MB/sec, SCSI (Small Computer System Interface) channels, etc. Consequently, for example, it is necessary that channel IF units or disk IF units for high throughput fiber optic channels and channel IF units or disk IF units for low throughput SCSI channels must be mounted in the same disk array controller and operated at the same time. For this purpose, therefore, it must be efficient to make an access between each of the channel IF units and/or the disk IF units provided with different types of interfaces and a cache memory.
Under the circumstances, it is an object of the present. invention to provide a disk array controller that can solve the above problems, that can make it possible to use every access path efficiently between each of the channel IF units and/or the disk IF units and a cache memory, and that will include a cache memory unit having a high throughput of data transfer.
In order to achieve the above objects, the disk array controller of the present invention includes a first channel interface unit for connecting a first host computer through a first type channel; a second channel interface unit for connecting a second host computer through a second type channel, which is different in type from the first type channel; a plurality of disk interface units having an interface with a magnetic disk unit, respectively; a cache memory connected to a plurality of the channel interface units and a plurality of the disk interface units and which is used for storing data to be read/written from/in the magnetic disk units temporarily; a shared memory connected to a plurality of the channel interface units and a plurality of disk interface units and which is used for storing control information related to data transfer between each of the channel interface units and/or the disk interface units and the cache memory. And, the disk array controller is composed so that the number of access paths connected to the cache memory is less than the number of access paths connected to the shared memory.
Preferably, the disk array controller should further include a selector unit connected to the first and second channel interface units, the disk interface units, and the cache memory. The first and second channel interface units and the disk interface unit are connected to the selector unit through an access path, respectively, in a one-by-one manner. The selector unit and the cache memory are also connected to each other through an access path. The total number of access paths for the connection between the first and second channel interface units and/or the disk interface unit and the selector unit is more than the total number of access paths for the connection between the selector unit and the cache memory unit. And, the first and second channel interface units and the disk interface units are connected to the selector unit and the shared memory through an access path, respectively, in a one-by-one manner.
The disk array controller should preferably be provided with a plurality of the selector units. The first channel interface units and the second channel interface units should be connected to different selector units.
Furthermore, the disk array controller of another embodiment is provided with a first channel interface unit for connecting a first host computer through a first type channel; a second channel interface unit for connecting a second host computer through a second type channel, which is different in type from the first type channel; a plurality of disk interface units having an interface with a magnetic disk unit, respectively; a cache memory connected to a plurality of the channel interface units and a plurality of the disk interface units and which is used for storing data to be read/written from/in the magnetic disk units; a shared memory connected to a plurality of the channel interface units and a plurality of the disk interface units and which is used for storing control data related to the data transfer between each of the channel interface units and/or the disk interface units and the cache memory. Each cache memory access controller and the cache memory is connected to each other by an access path through a selector unit and each shared memory access controller and the shared memory are connected to each other directly through an access path.
Furthermore, the disk array controller should preferably be composed so that the number of access paths for the connection between the first and second channel interface units and/or the disk interface units and the selector unit is equal to the number of access paths for the connection between the first and second channel interface units and/or the disk interface units and the shared memory unit. The number of access paths for the connection between the selector unit and the cache memory is less than the number of access paths for the connection between the first and second channel interface units and/or the disk interface units and the selector unit.
Furthermore, the disk array controller of another embodiment includes a first host interface group; a second host interface group; a first disk interface group; a second disk interface group; a first selector unit connected to the first host interface group and the disk interface group through a first access path; the second selector unit connected to the second host interface group and the first disk interface group through a second access path; and a cache memory connected to the first and second selector groups. In the disk array controller, the bandwidth of the first access paths is set equally to that of the second access paths.
Each of the first and second host interface groups should preferably include a host interface for the first type channels and a host interface for the second type channels, which is narrower than the bandwidth of the first type channels. Each of the first and second disk interface groups should preferably include a disk interface for the first type channels and a disk interface for the third type channels, which is narrower than the bandwidth of the first type channels.
The disk array controller of another embodiment is provided with a first selector unit, a second selector unit, and a cache memory connected to the first and second selector units. The first selector unit is connected to k (k: a natural number) host interface units for the first type channels; l (l: a natural number) host interfaces for the second type channels; m (m: a natural number) disk interface units for the first type channels; and n (n: a natural number) host interface units for the third type channels. The second selector unit is connected to k (k: a natural number) host interface units for the first type channels, which are different from the host interface units connected to the first selector unit; l (l: a natural number) host interfaces for the second type channels, which are different from the host interface units connected to the first selector unit; m (m: a natural number) disk interface units for the first type channels, which are different from the disk interface units connected to the first selector unit; and n (n: a natural number) host interface units for the third type channels, which are different from the disk interface units connected to the first selector unit.
The disk array controller of another embodiment is provided with a first selector unit connected only to host interface units for the first type channels and disk interface units for the first type channels; a second selector unit connected to host interface units for channels which are not the first type channels and disk interface units for channels which are not the first type channels; and a cache memory unit connected to the first and second selector units.
The bandwidth of the first type channels should preferably be wider than that of another type of channels, which are not the first type channels.
The bandwidth of the access path for connection between the first selector unit and the cache memory unit should preferably be wider than that for connection between the second selector unit and the cache memory unit.